Publication Type

Journal Article

Version

acceptedVersion

Publication Date

11-1987

Abstract

A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256K bit DRAM's are organized in 32K ?? 8 bit-bytes. Byte-oriented codes such as Reed-Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. In this correspondence we present a special decoding technique for double-byte-error-correcting (DBEC), triple-byte-error-detecting (TBED) RS codes which is capable of high-speed operation. This technique is designed to find the error locations and the error values directly from the syndrome without having to use the iterative algorithm to find the error locator polynomial.

Keywords

Byte error correction and detection, byte-organized memory systems, error control coding, Reed-Solomon codes, VLSI memory systems

Discipline

Information Security

Research Areas

Cybersecurity

Publication

IEEE Transactions on Computers

Volume

36

Issue

11

First Page

1359

Last Page

1363

ISSN

0018-9340

Identifier

10.1109/TC.1987.5009476

Publisher

IEEE

Copyright Owner and License

Authors

Additional URL

https://doi.org/10.1109/TC.1987.5009476

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