Decoding of DBEC-TBED Reed-Solomon Codes
A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256K bit DRAM's are organized in 32K ?? 8 bit-bytes. Byte-oriented codes such as Reed-Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. In this correspondence we present a special decoding technique for double-byte-error-correcting (DBEC), triple-byte-error-detecting (TBED) RS codes which is capable of high-speed operation. This technique is designed to find the error locations and the error values directly from the syndrome without having to use the iterative algorithm to find the error locator polynomial.
Information Security and Trust
IEEE Transactions on Computers
DENG, Robert H. and Costello, Jr., D. J..
Decoding of DBEC-TBED Reed-Solomon Codes. (1987). IEEE Transactions on Computers. 36, (11), 1359-1363. Research Collection School Of Information Systems.
Available at: http://ink.library.smu.edu.sg/sis_research/149